1. Field of the Invention
The present invention relates to integrated circuits and in particular to MOS integrated circuits. Still more particularly, the present invention relates to the suppression of latchup to a battery in a zero power circuit system.
2. Description of the Prior Art
In some situations, it is desirable to provide for retention of data in integrated circuits such as memory devices. A number of circuits are commercially available for retaining data in SRAMS when power is removed. An example of one such device may be found in U.S. Pat. No. 5,099.453, entitled Configuration Memory For Programmable Logic Device, U.S. Pat. No. 4,713,555, entitled Battery Charging Protection Circuit; U.S. Pat. No. 4,122,359, entitled Memory Protection Arrangement; and U.S. Pat. No. 4,451,742, entitled Power Supply Control For Integrated Circuit. These devices are often known as "zero power circuits". Typically, in a zero power circuit, the contents of the circuit are protected in the event that the power supply voltage to that circuit drops below some predetermined or selected threshold voltage. This protection may be accomplished by switching the circuit from a primary power supply to a secondary power supply, typically an integral battery, when the voltage of the primary power supply drops below the selected threshold voltage.
Power control circuits exist which provide automatic sensing of a primary power source voltage. These power control circuits provide for automatic switching to a secondary power source when the primary power source voltage drops below a predetermined threshold voltage. A resistor is typically placed in series with the pad connecting the circuit to the battery. The resistor is a common industry requirement used to suppress latchup to the battery. If latchup were to occur, the sustaining current would drop most of the battery voltage across the resistor, and as a result, latchup would not be sustained.
Referring to FIG. 1, a block diagram of a zero power static random access memory (SRAM) chip is illustrated. Chip 10 includes a pad 12 that leads to the VCC pin of the chip and a pad 14, which is connected to a battery. The battery may be contained in the packaging of the chip or off the chip. Pads 12 and 14 are connected to power control circuit 16, also called a "switching circuit". Resistor 18 is placed between pad 14 and power control circuit 16 to suppress latchup to the battery. Power control circuit 16 controls the supply of power to SRAM 20 and input/output (I/O) circuits 22 and 24. I/O circuits 22 and 24 may include, for example, I/O buffers. In the event that the power supply VCC drops below a predetermined threshold at pad 12, power control circuit 16 switches to pad 14 to provide power to chip 10. In addition, power control circuit 16 may disable nonessential circuitry such as I/O circuits 22 and 24 while maintaining power to SRAM 20.
When chips are surface mounted, the high temperatures resulting from the surface mount procedure may cause high leakage currents that could potentially drop all of the battery voltage across resistor 18. The loss of power may cause a loss of data previously programmed into SRAM 20.
Therefore, it would be desirable to have a method and apparatus for preventing loss of power to a zero power circuit containing data during surface mount operations or during other events that may cause high leakage currents to occur.